Neural processing unit (npu) direct memory access (ndma) memory bandwidth optimization

ABSTRACT

A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.

BACKGROUND Field

Certain aspects of the present disclosure generally relate to convolutional neural networks and, more particularly, to a neural processing unit (NPU) direct memory access (NDMA) bandwidth optimization for artificial neural networks.

Background

An artificial neural network, which may be composed of an interconnected group of artificial neurons (e.g., neuron models), is a computational device or represents a method performed by a computational device. These neural networks may be used for various applications and/or devices, such as Internet Protocol (IP) cameras, Internet of Things (IoT) devices, autonomous vehicles, and/or service robots.

Convolutional neural networks are a type of feed-forward artificial neural network. Convolutional neural networks may include collections of neurons that each have a receptive field and that collectively tile an input space. Convolutional neural networks (CNNs) have numerous applications. In particular, CNNs have broadly been used in the area of pattern recognition and classification.

In layered neural network architectures, the output of a first layer of neurons becomes an input to a second layer of neurons, the output of a second layer of neurons becomes an input to a third layer of neurons, and so on. Convolutional neural networks may be trained to recognize a hierarchy of features. Computation in convolutional neural network architectures may be distributed over a population of processing nodes, which may be configured in one or more computational chains. These multi-layered architectures may be trained one layer at a time and may be fine-tuned using back propagation.

Convolutional neural networks, however, tend to shrink input features during computations through the various network layers. Shrinking of the input feature size during computations fails to preserve an original size of the input features. Input feature padding may be used to preserve the input feature size during computations though the neural network layers. Although input feature padding preserves the input feature size, processing of the padded values unduly increases memory bandwidth utilization in deep convolutional neural networks.

SUMMARY

A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.

A method for hardware-based memory bandwidth optimization of a neural processing unit (NPU) direct memory access (NDMA) in artificial neural networks is described. The method includes programming configuration registers of a neural processing unit (NPU) direct memory access (NDMA) core for a read client and/or a write client. The method also includes transparently combining NDMA transaction requests from the read client and/or the write client as a single NDMA transaction request. The method further includes streaming data blocks of data stripes of the single NDMA transaction request. The data blocks are streamed to/from an external memory of the NDMA core and to/from the read client and/or the write client.

An artificial neural network for hardware-based memory bandwidth optimization of a neural processing unit (NPU) direct memory access (NDMA) is described. The artificial neural network includes means for programming configuration registers of a neural processing unit (NPU) direct memory access (NDMA) core for a read client and/or a write client. The artificial neural network also includes means for transparently combining NDMA transaction requests from the read client and/or the write client as a single NDMA transaction request. The artificial neural network further includes means for streaming data blocks of data stripes of the single NDMA transaction request. The data blocks of the data stripes are streamed to/from an external memory of the NDMA core and to/from the read client and/or the write client.

A non-transitory computer-readable medium having program code recorded thereon for hardware-based memory bandwidth optimization of a neural processing unit (NPU) direct memory access (NDMA) is described. The program code is executed by a processor. The computer-readable medium includes program code to program configuration registers of a neural processing unit (NPU) direct memory access (NDMA) core for a read client and/or a write client. The computer-readable medium also includes program code to transparently combine NDMA transaction requests from the read client and/or the write client as a single NDMA transaction request. The computer-readable medium further includes program code to stream data blocks of data stripes of the single NDMA transaction request. The data blocks of the data stripes are streamed to/from an external memory of the NDMA core and to/from the read client and/or the write client.

This has broadly outlined the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, nature, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

FIG. 1 illustrates an example implementation of a system-on-a-chip (SOC), including a general-purpose processor, in accordance with certain aspects of the present disclosure.

FIGS. 2A, 2B, and 2C are diagrams illustrating a neural network, in accordance with aspects of the present disclosure.

FIG. 2D is a diagram illustrating an exemplary deep convolutional neural network (DCNN), in accordance with aspects of the present disclosure.

FIG. 3 is a block diagram illustrating an exemplary deep convolutional neural network (DCNN), in accordance with aspects of the present disclosure.

FIG. 4 is a block diagram illustrating an exemplary software architecture that may modularize artificial intelligence (AI) functions, in accordance with aspects of the present disclosure.

FIG. 5A is a block diagram of an image partitioned into M-stripes, according to aspects of the present disclosure.

FIG. 5B is a block diagram illustrating parameters of a stripe image, according to aspects of the present disclosure.

FIG. 5C is a block diagram illustrating further parameters of the stripe image of an original image of FIG. 5B, according to aspects of the present disclosure.

FIG. 6A is a block diagram illustrating storage of a two-dimensional (2D) data block in an external memory, according to aspects of the present disclosure.

FIG. 6B is a block diagram illustrating a three-dimensional representation of image data, according to aspects of the present disclosure.

FIG. 7 is a block diagram illustrating a neural processing unit (NPU), including an NPU direct memory access (NDMA) core and interfaces configured to provide hardware pre-processing and post-processing of NDMA data, according to aspects of the present disclosure.

FIG. 8 is a block diagram, further illustrating the NDMA core of FIG. 7, in which the read engine is configured in a multi-buffer mode, according to aspects of the present disclosure.

FIG. 9 is a block diagram, illustrating a three-dimensional (3D) data structure, in which a data concatenation operation is performed, according to aspects of the present disclosure.

FIG. 10 is a block diagram, illustrating a memory, in which data compression is performed, according to aspects of the present disclosure.

FIGS. 11A and 11B are block diagrams of three-dimensional (3D) data structures illustrating a partial stripe mode, according to aspects of the present disclosure.

FIG. 12 illustrates a method for hardware-based memory bandwidth optimization of neural processing unit (NPU) direct memory access (NDMA), in accordance with aspects of the present disclosure.

FIG. 13 further illustrates a method for hardware-based memory bandwidth optimization of neural processing unit (NPU) direct memory access (NDMA), in accordance with aspects of the present disclosure.

DETAILED DESCRIPTION

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

Based on the teachings, one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth. In addition, the scope of the disclosure is intended to cover such an apparatus or method practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth. It should be understood that any aspect of the disclosure disclosed may be embodied by one or more elements of a claim.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

Although particular aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different technologies, system configurations, networks and protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the disclosure rather than limiting the scope of the disclosure being defined by the appended claims and equivalents thereof.

Deep learning neural networks, having either convolutional or fully connected layers, enable processing for image recognition, object detection, and natural language processing. These features also enable support for autonomous driving applications as well as content-aware camera processing. Deep convolutional networks (DCNNs) have promising applications in emerging embedded, wearable, and Internet of Things (IoT) markets.

In operation, a deep convolutional neural network (or DCNN) may be composed of a large number of weight tensors multiplied by activation tensors. These weight tensors and activation tensors enable multiplying of input data by weights in various filters of the DCNN. In a previous layer of the DCNN, the activation tensors may be fed through nonlinear functions. In operation, processing in DCNNs generally involves convolution of weight tensors and activation tensors to perform tasks.

DCNNs consume a significant amount of memory bandwidth loading the large number of weight tensors and activation tensors for performing convolution operations. In particular, processing of the tensors from various network layers in deep convolutional neural networks unduly increases memory bandwidth utilization by neural processing units (NPUs). Direct memory access may be used by the NPUs during processing of the activation tensors to improve memory bandwidth utilization in deep convolutional neural networks.

Aspects of the present disclosure are directed to a neural processing unit (NPU) direct memory access (NDMA) memory bandwidth optimization using programmable hardware features for deep convolutional neural networks (DCNNs). NDMA hardware optimizations enable efficient utilization of memory transfers and locality in the computation, resulting in superior resource utilization and energy efficiency. In operation, a size of tensors (e.g., activations and weights) processed by an NPU is generally less than a capacity of available memory bandwidth from external memory. In aspects of the present disclosure, transactions requesting NDMA data may be transparently combined into a single NDMA transaction, with the requested NDMA data stored into NDMA queues. Transparently combining transactions requesting NDMA data beneficially reduces the number of transactions issued to the external memory. Transparently combining NDMA transactions also increases throughput as well as computations by increasing the amount of NDMA data (e.g., tensors) available for NPU operations.

As described, the term NDMA data may refer to data (e.g., image data, activation tensors, or other like convolutional data) moved from external (e.g., main) memory to storage closer to the compute units of an NPU (e.g., read clients and/or write clients). NDMA hardware optimization (e.g., transparently combining NDMA transaction requests) is software programmable, which ultimately results in better resource utilization and energy efficiency. In aspects of the present disclosure, programmability of the hardware-based memory bandwidth optimization is provided at a grain level of a layer in the neural network.

FIG. 1 illustrates an example implementation of a system-on-a-chip (SOC) 100, which may include a neural processing unit (NPU) 108 or a multi-core NPU configured to perform hardware-based memory bandwidth optimization for NPU direct memory access (NDMA) in accordance with certain aspects of the present disclosure. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computational device (e.g., neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with an NPU 108, in a memory block associated with a central processing unit (CPU) 102, in a memory block associated with a graphics processing unit (GPU) 104, in a memory block associated with a digital signal processor (DSP) 106, in a memory block 118, or may be distributed across multiple blocks. Instructions executed at the CPU 102 may be loaded from a program memory associated with the CPU 102 or may be loaded from a memory block 118.

The SOC 100 may also include additional processing blocks tailored to specific functions, such as a connectivity block 110, which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, and the like, and a multimedia processor 112 that may, for example, detect and recognize gestures. In one implementation, the NPU is implemented in the CPU, DSP, and/or GPU. The SOC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, and/or navigation module 120, which may include a global positioning system.

The NPU 108 may be based on an ARM instruction set. In an aspect of the present disclosure, the instructions loaded into the NPU 108 may comprise code to program configuration registers of a neural processing unit (NPU) direct memory access (NDMA) core for a read client and/or a write client. The instructions loaded into the NPU 108 may also comprise code to transparently combine NDMA transaction requests from the read client and/or the write client as a single NDMA transaction request. In addition, the instructions loaded into the NPU 108 may comprise code to stream data blocks of data stripes of the single NDMA transaction request, the data blocks being streamed to/from an external memory of the NDMA core and to/from the read client and/or the write client.

Deep learning architectures may perform an object recognition task by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building up a useful feature representation of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Prior to the advent of deep learning, a machine learning approach to an object recognition problem may have relied heavily on human engineered features, perhaps in combination with a shallow classifier. A shallow classifier may be a two-class linear classifier, for example, in which a weighted sum of the feature vector components may be compared with a threshold to predict to which class the input belongs. Human engineered features may be templates or kernels tailored to a specific problem domain by engineers with domain expertise. Deep learning architectures, in contrast, may learn to represent features that are similar to what a human engineer might design, but through training. Furthermore, a deep network may learn to represent and recognize new types of features that a human might not have considered.

A deep learning architecture may learn a hierarchy of features. If presented with visual data, for example, the first layer may learn to recognize relatively simple features, such as edges, in the input stream. In another example, if presented with auditory data, the first layer may learn to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, may learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For instance, higher layers may learn to represent complex shapes in visual data or words in auditory data. Still higher layers may learn to recognize common visual objects or spoken phrases.

Deep learning architectures may perform especially well when applied to problems that have a natural hierarchical structure. For example, the classification of motorized vehicles may benefit from first learning to recognize wheels, windshields, and other features. These features may be combined at higher layers in different ways to recognize cars, trucks, and airplanes.

Neural networks may be designed with a variety of connectivity patterns. In feed-forward networks, information is passed from lower to higher layers, with each neuron in a given layer communicating to neurons in higher layers. A hierarchical representation may be built up in successive layers of a feed-forward network, as described above. Neural networks may also have recurrent or feedback (also called top-down) connections. In a recurrent connection, the output from a neuron in a given layer may be communicated to another neuron in the same layer. A recurrent architecture may be helpful in recognizing patterns that span more than one of the input data chunks that are delivered to the neural network in a sequence. A connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. A network with many feedback connections may be helpful when the recognition of a high-level concept may aid in discriminating the particular low-level features of an input.

The connections between layers of a neural network may be fully connected or locally connected. FIG. 2A illustrates an example of a fully connected neural network 202. In a fully connected neural network 202, a neuron in a first layer may communicate its output to every neuron in a second layer, so that each neuron in the second layer will receive input from every neuron in the first layer. FIG. 2B illustrates an example of a locally connected neural network 204. In a locally connected neural network 204, a neuron in a first layer may be connected to a limited number of neurons in the second layer. More generally, a locally connected layer of the locally connected neural network 204 may be configured so that each neuron in a layer will have the same or a similar connectivity pattern, but with connection strengths that may have different values (e.g., 210, 212, 214, and 216). The locally connected connectivity pattern may give rise to spatially distinct receptive fields in a higher layer, because the higher layer neurons in a given region may receive inputs that are tuned through training to the properties of a restricted portion of the total input to the network.

One example of a locally connected neural network is a convolutional neural network. FIG. 2C illustrates an example of a convolutional neural network 206. The convolutional neural network 206 may be configured such that the connection strengths associated with the inputs for each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be well suited to problems in which the spatial location of inputs is meaningful.

One type of convolutional neural network is a deep convolutional neural network (DCNN). FIG. 2D illustrates a detailed example of a DCNN 200 designed to recognize visual features from an image 226 input from an image capturing device 230, such as a car-mounted camera. The DCNN 200 of the current example may be trained to identify traffic signs and a number provided on the traffic sign. Of course, the DCNN 200 may be trained for other tasks, such as identifying lane markings or identifying traffic lights.

The DCNN 200 may be trained with supervised learning. During training, the DCNN 200 may be presented with an image, such as the image 226 of a speed limit sign, and a forward pass may then be computed to produce an output 222. The DCNN 200 may include a feature extraction section and a classification section. Upon receiving the image 226, a convolutional layer 232 may apply convolutional kernels (not shown) to the image 226 to generate a first set of feature maps 218. As an example, the convolutional kernel for the convolutional layer 232 may be a 5×5 kernel that generates 28×28 feature maps. In the present example, because four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels were applied to the image 226 at the convolutional layer 232. The convolutional kernels may also be referred to as filters or convolutional filters.

The first set of feature maps 218 may be subsampled by a max pooling layer (not shown) to generate a second set of feature maps 220. The max pooling layer reduces the size of the first set of feature maps 218. That is, a size of the second set of feature maps 220, such as 14×14, is less than the size of the first set of feature maps 218, such as 28×28. The reduced size provides similar information to a subsequent layer while reducing memory consumption. The second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

In the example of FIG. 2D, the second set of feature maps 220 is convolved to generate a first feature vector 224. Furthermore, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number that corresponds to a possible feature of the image 226, such as “sign,” “60,” and “100.” A softmax function (not shown) may convert the numbers in the second feature vector 228 to a probability. As such, an output 222 of the DCNN 200 is a probability of the image 226 including one or more features.

In the present example, the probabilities in the output 222 for “sign” and “60” are higher than the probabilities of the others of the output 222, such as “30,” “40,” “50,” “70,” “80,” “90,” and “100”. Before training, the output 222 produced by the DCNN 200 is likely to be incorrect. Thus, an error may be calculated between the output 222 and a target output. The target output is the ground truth of the image 226 (e.g., “sign” and “60”). The weights of the DCNN 200 may then be adjusted so the output 222 of the DCNN 200 is more closely aligned with the target output.

To adjust the weights, a learning algorithm may compute a gradient vector for the weights. The gradient may indicate an amount that an error would increase or decrease if the weight were adjusted. At the top layer, the gradient may correspond directly to the value of a weight connecting an activated neuron in the penultimate layer and a neuron in the output layer. In lower layers, the gradient may depend on the value of the weights and on the computed error gradients of the higher layers. The weights may then be adjusted to reduce the error. This manner of adjusting the weights may be referred to as “back propagation” as it involves a “backward pass” through the neural network.

In practice, the error gradient of weights may be calculated over a small number of examples, so that the calculated gradient approximates the true error gradient. This approximation method may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the achievable error rate of the entire system has stopped decreasing or until the error rate has reached a target level. After learning, the DCNN may be presented with new images (e.g., the speed limit sign of the image 226) and a forward pass through the network may yield an output 222 that may be considered an inference or a prediction of the DCNN.

Deep belief networks (DBNs) are probabilistic models comprising multiple layers of hidden nodes. DBNs may be used to extract a hierarchical representation of training data sets. A DBN may be obtained by stacking up layers of Restricted Boltzmann Machines (RBMs). An RBM is a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn a probability distribution in the absence of information about the class to which each input should be categorized, RBMs are often used in unsupervised learning. Using a hybrid unsupervised and supervised paradigm, the bottom RBMs of a DBN may be trained in an unsupervised manner and may serve as feature extractors, and the top RBM may be trained in a supervised manner (on a joint distribution of inputs from the previous layer and target classes) and may serve as a classifier.

Deep convolutional neural networks (DCNNs) are networks of convolutional networks, configured with additional pooling and normalization layers. DCNNs have achieved state-of-the-art performance on many tasks. DCNNs can be trained using supervised learning in which both the input and output targets are known for many exemplars and are used to modify the weights of the network by use of gradient descent methods.

DCNNs may be feed-forward networks. In addition, as described above, the connections from a neuron in a first layer of a DCNN to a group of neurons in the next higher layer are shared across the neurons in the first layer. The feed-forward and shared connections of DCNNs may be exploited for fast processing. The computational burden of a DCNN may be much less, for example, than that of a similarly sized neural network that comprises recurrent or feedback connections.

The processing of each layer of a convolutional network may be considered a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on that input may be considered three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information. The outputs of the convolutional connections may be considered to form a feature map in the subsequent layer, with each element of the feature map (e.g., 220) receiving input from a range of neurons in the previous layer (e.g., feature maps 218) and from each of the multiple channels. The values in the feature map may be further processed with a non-linearity, such as a rectification, max(0,x). Values from adjacent neurons may be further pooled, which corresponds to down sampling, and may provide additional local invariance and dimensionality reduction. Normalization, which corresponds to whitening, may also be applied through lateral inhibition between neurons in the feature map.

The performance of deep learning architectures may increase as more labeled data points become available or as computational power increases. Modern deep neural networks are routinely trained with computing resources that are thousands of times greater than what was available to a typical researcher just fifteen years ago. New architectures and training paradigms may further boost the performance of deep learning. Rectified linear units may reduce a training issue known as vanishing gradients. New training techniques may reduce over-fitting and thus enable larger models to achieve better generalization. Encapsulation techniques may abstract data in a given receptive field and further boost overall performance.

FIG. 3 is a block diagram illustrating a deep convolutional network 350. The deep convolutional neural network 350 may include multiple different types of layers based on connectivity and weight sharing. As shown in FIG. 3, the deep convolutional neural network 350 includes the convolution blocks 354A, 354B. Each of the convolution blocks 354A, 354B may be configured with a convolution layer (CONV) 356, a normalization layer (LNorm) 358, and a max pooling layer (MAX POOL) 360.

The convolution layers 356 may include one or more convolutional filters, which may be applied to the input data to generate a feature map. Although only two of the convolution blocks 354A, 354B are shown, the present disclosure is not so limiting, and instead, any number of the convolution blocks 354A, 354B may be included in the deep convolutional neural network 350 according to design preference. The normalization layer 358 may normalize the output of the convolution filters. For example, the normalization layer 358 may provide whitening or lateral inhibition. The max pooling layer 360 may provide down sampling aggregation over space for local invariance and dimensionality reduction.

The parallel filter banks, for example, of a deep convolutional neural network may be loaded on a CPU 102 or GPU 104 of an SOC 100 to achieve high performance and low power consumption. In alternative embodiments, the parallel filter banks may be loaded on the DSP 106 or an ISP 116 of an SOC 100. In addition, the deep convolutional neural network 350 may access other processing blocks that may be present on the SOC 100, such as the sensor processor 114 and navigation module 120, dedicated, respectively, to sensors and navigation.

The deep convolutional neural network 350 may also include one or more fully connected layers 362 (FC1 and FC2). The deep convolutional neural network 350 may further include a logistic regression (LR) layer 364. Between each layer 356, 358, 360, 362, 364 of the deep convolutional neural network 350 are weights (not shown) that are to be updated. The output of each of the layers (e.g., 356, 358, 360, 362, 364) may serve as an input of a succeeding one of the layers (e.g., 356, 358, 360, 362, 364) in the deep convolutional neural network 350 to learn hierarchical feature representations from input data 352 (e.g., images, audio, video, sensor data, and/or other input data) supplied at the first of the convolution blocks 354A. The output of the deep convolutional neural network 350 is a classification score 366 for the input data 352. The classification score 366 may be a set of probabilities, where each probability is the probability of the input data including a feature from a set of features.

FIG. 4 is a block diagram illustrating an exemplary software architecture 400 that may modularize artificial intelligence (AI) functions. Using the architecture, applications may be designed that may cause various processing blocks of an SOC 420 (for example a CPU 422, a DSP 424, a GPU 426, and/or an NPU 428) to support hardware-based memory bandwidth optimization for NPU direct memory access (NDMA) during run-time operation of an AI application 402, according to aspects of the present disclosure.

The AI application 402 may be configured to call functions defined in a user space 404 that may, for example, provide for the detection and recognition of a scene indicative of the location in which the device currently operates. The AI application 402 may, for example, configure a microphone and a camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor setting such as a lake. The AI application 402 may make a request to compiled program code associated with a library defined in an AI function application programming interface (API) 406. This request may ultimately rely on the output of a deep neural network configured to provide an inference response based on video and positioning data, for example.

A run-time engine 408, which may be compiled code of a runtime framework, may be further accessible to the AI application 402. The AI application 402 may cause the run-time engine, for example, to request an inference at a particular time interval or triggered by an event detected by the user interface of the application. When caused to provide an inference response, the run-time engine may in turn send a signal to an operating system in an operating system (OS) space 410, such as a Linux Kernel 412, running on the SOC 420. The operating system, in turn, supports hardware-based memory bandwidth optimization for NPU direct memory access (NDMA) performed on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof. The CPU 422 may be accessed directly by the operating system, and other processing blocks may be accessed through a driver, such as a driver 414, 416, or 418 for, respectively, the DSP 424, the GPU 426, or the NPU 428. In the exemplary example, the deep neural network may be configured to run on a combination of processing blocks, such as the CPU 422, the DSP 424, and the GPU 426, or may be run on the NPU 428.

Referring again to FIG. 1, the SOC 100 includes a neural processing unit (NPU) 108 or a multi-core NPU configured to perform hardware-based memory bandwidth optimization for NPU direct memory access (NDMA), in accordance with certain aspects of the present disclosure. In aspects of the present disclosure, an NDMA core of the NPU 108 is configured to move substantial chunks of data (e.g., an image frame of one-dimensional (1D), two-dimensional (2D), or three-dimensional (3D) data and/or activation tensors). In aspects of the present disclosure, the NDMA core moves the data chunks in and out of an array of compute elements of the NPU 108 (e.g., read clients and/or write clients) by streaming the data. During streaming of the data, the NDMA core may perform hardware pre-processing and post-processing during reading/writing of the data streaming to/from client buffers.

In aspects of the present disclosure, streaming of data refers to movement of data in a stripe, block by block, in response to a single NDMA command. That is, streaming of data moves a small block (e.g., 1D, 2D, or 3D) at a time, and continues by moving another block after a period of time (e.g., to receive a bus grant signal). This process is repeated until a stripe of data is moved to/from a client buffer. In this example, the block size is programmable, which will generally be larger than a bus transaction size. In aspects of the present disclosure, the NDMA core of the NPU 108 can be configured to move a stripe of data (e.g., multiple blocks), for example as shown in FIGS. 5A, 5B, and 5C.

FIG. 5A is a block diagram of an image 500 partitioned into M-stripes, according to aspects of the present disclosure. Traditional streaming retrieves a chunk of memory aligned with the boundaries of main memory and stores the chunk of memory locally. Aspects of the present disclosure recognize that tensor computations in deep learning neural networks generally do not involve the entire chunk of memory, such as the image 500. Generally, a subset of the chunk of data is used for tensor computation in deep learning neural networks. According to aspects of the present disclosure, this subset of data may be a stripe of the image 500.

As described, striping is a data processing technique in which an image 500 is partitioned into any desirable number of vertical slices (e.g., stripe 0, stripe 1, . . . , stripe m−1). In this example, the image 500, including N-lines (e.g., line 0, line 1, line n−1), is carved into M-vertical slices. Each vertical slice is referred as a stripe (e.g., a stripe image or data stripe). In one example, the image 500 is an m-sliced image, in which the line width of the image 500 is partitioned into m line segments, which may or may not equal the N-lines of the image 500. That is, the height of each stripe (e.g., stripe 0, stripe 1, . . . , stripe m−1), in most cases, matches the height of the image 500. There is, however, no restriction mandating every stripe having an equal width or having a height equal to the height of the image 500.

FIG. 5B is a block diagram illustrating parameters of a stripe image 560 of an original image 550, according to aspects of the present disclosure. Striping operates on an established coordinate system, allowing software users to specify the dimension and location of a sliced image (e.g., image 500 of FIG. 5A). The parameters of the stripe image 560 can be described in the context of high-level system design or a low-level hardware implementation. For example, from a high-level system perspective, the start location of the stripe image 560 may be specified in terms of an x_offset and a y_offset. The x_offset is the horizontal displacement between the left-most side of the stripe image 560 and the left-most side of the original image 550, measured in terms of pixels. The y_offset is the vertical displacement between the top-most side of the stripe image 560 and the top-most side of the original image 550, measured in terms of line numbers.

Additional parameters include an image_width (e.g., the width of the original image 550), image_height (e.g., the height of the original image 550), a start_address (e.g., the starting location (e.g., address) of the stripe in external memory), an x_size (e.g., the width of the stripe), and a y_size (e.g., the height of the stripe). While pixel and line representation is one option for specifying the location of the stripe image 560, this representation can be difficult and expensive to implement in hardware. For this reason, software users are expected to convert the parameters specified in a system domain into a hardware domain (e.g., the memory address of the pixel words) for reducing hardware complexity and cost. Regardless of the specified parameters, NDMA enables stripe read and stripe write for accessing NDMA data.

FIG. 5C is a block diagram 580 illustrating further parameters of the stripe image 560 of the original image 550 of FIG. 5B, according to aspects of the present disclosure. Conceptually, stripe-based processing is a subset of block-based processing. Consequently, the block parameters of the stripe image 560 may be specified in terms of a block 590, which is the smallest group of data moved by a single direct memory access (DMA) channel arbitration. The block parameters include a blk_start_addr, a blk_size, a last_blk_size, an x_side_dword, a num_blks parameter, and a row_incr parameter. The blk_start_addr parameter is the external memory address of each block at the start point. The blk_size and the last_blk_size parameters are used to define the size of the stripe image 560. The blocks of the stripe image 560 generally have the same size, except for the last block, which has the last_blk_size. The num_blks parameter indicates the number (e.g., a predetermined number) of blocks in the stripe image 560. The x_size_dword parameter is the word size of the block 590. The row_incr parameter is a block address increment used to determine a next block's address by adding to the previous start address (e.g., blk_start_addr). As described, address hopping is a data access technique for accessing blocks within a stripe image (e.g., 560).

During block streaming to stripe read and/or stripe write, data is saved to an external memory (e.g., double data rate (DDR) memory) in a 2D fashion. In particular, image data, such as the image 500 shown in FIG. 5A, is understood to represent a 2D format. During NDMA operation, a stripe of data can be accessed from the 2D data block (e.g., block 590 shown in FIG. 5C). In practice, data is stored in the external (e.g., DDR) memory using a contiguous address space. 2D and 3D data may be accessed using address hopping, for example, as shown in FIGS. 6A and 6B.

FIG. 6A is a block diagram illustrating storage of a 2D data block 600 in an external memory, according to aspects of the present disclosure. The 2D data block 600 includes N-lines (e.g., line 0, . . . , line n−1) and is defined by a data_width parameter, a data_height parameter, and block address parameters (e.g., block_addr0_0, block_addr0_m, block_addrn_0, and block_addrn_m). The 2D data block 600 includes a stripe 610 defined by stripe_start_addr, x_offset, y_offset, x_size, and y_size parameters.

FIG. 6B is a block diagram illustrating a three-dimensional representation of image data, according to aspects of the present disclosure. In particular, a 3D data structure 650 is shown. In this example, data is stored in an external memory in a raster order of lines in a Dim0 direction (in pixels), and continuously in a Dim1 direction. The 3D data storage is repeated over Dim0-Dim1 raster order in a Dim2 direction. The 3D data storage format can be described as a 3D array (e.g., DDR_data[dim2][dim1][dim0]). Data access to a stripe of 3D rectangular blocks is performed in a predetermined order, for example, by repeating access over the Dim0 and Dim1 directions, and proceeding in raster order over the Dim2 direction.

As described, Dim0 refers to a dimension that moves sequentially through contiguous NDMA words (e.g., a dword or a 256-bit word) in external memory; the term Dim1 refers to a dimension used when data is transferred in a 3D block (e.g., as shown in FIG. 6B) and the term Dim2 refers to a dimension used when data is transferred as a 2D or 3D block. As further described, the terms “lines” and “rows” are used interchangeably to describe aspects of the present disclosure because both terms refer to the lines of an image. Strictly speaking, however, “line” refers to the main image, while “row” refers to the lines contained in a given read buffer (e.g., one stripe).

FIG. 7 is a block diagram illustrating an NPU 700, including an NPU DMA (NDMA) core 710 and interfaces configured to provide hardware-based memory bandwidth optimization for NPU direct memory access (NDMA), according to aspects of the present disclosure. The NDMA core 710 includes a read engine 720 configured to provide a first memory interface to a read client (RCLT) and a write engine 730 configured to provide a second memory interface to a write client (WCLT). The memory interfaces to the client side (e.g., RCLT, WCLT) are memory read/write interfaces using a request/valid handshake. In aspects of the present disclosure, the read client RCLT and the write client WCLT may refer to an array to compute elements of the NPU 700, which may support, for example, 16-NDMA read channels and 16-NDMA write channels for the various compute units of the NPU 700.

The NDMA core 710 also includes a bus interface (e.g., a synchronous media and switch fabric (MSF) interface) to a bus bridge 740. In this configuration, the NDMA core 710 is connected to the bus bridge 740 as well as a network on chip (NoC) 750, such as a multimedia subsystem (MMSS) NoC. In this configuration, the NoC 750 includes a deep learning bandwidth compression (DLBC) block 752, configured to perform compression (e.g., lossy compression) of NDMA data. The bus bridge 740 may be connected to the NoC 750 using, for example, an advance eXtensible interface (AXI). The NoC 750 may be connected to an external memory 760 (e.g., a DDR memory) through an external memory interface (e.g., an AXI bus).

In this configuration, the NDMA core 710 is partitioned into two major logic components; namely the write engine 730 and the read engine 720. The write engine 730 is configured to move processed client data to the external memory 760 in a stripe format (see FIGS. 5A-5C). On the other hand, the read engine 720 is configured to transfer fragmented data from the external memory 760 into client memories (e.g., read buffer 722 and/or write buffer 732) for image processing or for configuration. The write client WCLT and the read client RCLT are independent of each other.

As described, a write path implies an NDMA read from the write client WCLT and a write to the external memory 760, and a read path implies an NDMA read from the external memory 760 and a write to the read client RCLT. In addition, the terms “read path,” “read client,” and “read channel” are used interchangeably. The terms “write path,” “write client,” and “write channel” are also used interchangeably.

In this aspect of the present disclosure, the NDMA core 710 avoids using large NDMA buffers. Instead, the NDMA core 710 may rely on client buffers of the read client RCLT and the write client WCLT for buffering NDMA data. This configuration provides flexibility by reusing the client's buffers from NDMA data transfer. In this configuration, the read engine 720 includes a read buffer 722 for storing (e.g., a bus width of) configuration data. The read engine 720 is configured to read 256-bits of configuration data from the read buffer 722 that is used for configuration of NDMA operation for the read client RCLT and/or the write client WCLT.

In operation, the read engine 720 retrieves (e.g., one bus width number of) bits of image data (e.g., NDMA data) from the external memory 760 and stores those bits in the read buffer 722. According to aspects of the present disclosure, the stored bits of image data may be subjected to programmable hardware memory bandwidth optimization within the read buffer. As described, processing of NDMA data while stored in the read buffer 722 may refer to hardware read optimization of the NDMA data, whereas processing of the NDMA data in the write buffer 732 may refer to hardware write optimization of the NDMA data.

As further shown in FIG. 7, the write engine 730 is configured to perform a 3D rectangle stripe write, a 2D rectangle stripe write, or a normal write to the external memory 760 in a streaming fashion (e.g., block by block). In this example, the write engine 730 is configured to retrieve 128-bits of data from the client buffer of the write client WCLT, pack to 64-bits word aligned (e.g., image pixel packing), form a dual word (128-bits) and write to the write buffer 732. When data in the write buffer 732 has reached a completed transaction size (e.g., the number of beats per transaction is programmable), this NDMA data is read out of the write buffer 732 and sent out to the bus bridge 740 through a write arbiter 714 to write to the external memory 760 as, for example, a 256-bit data word. The write arbiter 714 and a read arbiter 712 may operate according to a round robin arbitration between different NDMA read channels or NDMA write channels. The NDMA read channels and the NDMA write channels are independent.

A controller 770 is provided as a configuration interface of the NDMA core 710. In aspects of the present disclosure, the controller 770 configures parameters for block data movement. In addition, the controller 770 configures parameters for performing hardware-based memory bandwidth optimization for NDMA, including a multi-buffer mode, a minimum access length (MAL) boundary restriction, a partial reset operation, concatenated/re-concatenated data movement operation, multi-block operation mode, deep learning bandwidth compression (DLBC), and partial-stripe mode. The controller 770 may configure registers (e.g., register ports) of the NPU 700 to direct the NDMA core 710 during hardware-based memory optimization of the NDMA. Multi-buffer mode may be configured, for example, as shown in FIG. 8.

FIG. 8 is a block diagram 800, further illustrating the NDMA core 710, in which the read engine 720 is configured in a multi-buffer configuration, according to aspects of the present disclosure. In this configuration, the read buffer 722 of the read engine 720 is partitioned into a first buffer Buf_0 and a second buffer Buf_1. Although shown as the read buffer 722, it should be recognized that the multi-buffer configuration may be provided as a part of a NDMA queue (not shown) of the NDMA core 710, or other like local cache or buffer NDMA. The read buffer 722 includes several NDMA data blocks (e.g., NDMA data block_1, NDMA data block_m, and NDMA data block_n). In addition, although two buffers are shown, it should be recognized that additional buffers are contemplated.

In the multi-buffer configuration shown in FIG. 8, an NDMA read path of the NDMA core 710 supports a two buffer mode to enable streaming of scattered memory location. For example, the NDMA data block_m crosses a buffer boundary between the first buffer Buf_0 and the second buffer Buf_1. In practice, it is likely that a full image may be stored across multiple fragments of external memory (e.g., external memory 760 of FIG. 7). Crossing of the buffer boundary between the first buffer Buf_0 and the second buffer Buf_1, therefore, results in fragmented storage of image data in the external memory.

In this aspect of the present disclosure, the read engine 720 is configured to independently perform a stripe image read from a scattered memory location (e.g., NDMA data blocks), such that scattered locations of external memory 760 appear as one contiguous space for the read client RCLT (shown in FIG. 7). In this example, the first buffer Buf_0 and the second buffer Buf_1 are adjacent. These two buffers, however, may be non-adjacent. That is, the second buffer's start address can be anywhere in the read buffer 722. The multi-buffer mode, however, specifies that any line in a Dim0 direction cannot cross the buffer boundary. Parameters of the multi-buffer mode include a frag_0_addr (e.g., start address of the first valid data in Buf_0), end_addr_0 (e.g., end address of last valid data in Buf_0), max_addr_0 (e.g., maximum read address where the allocated fragment Buf_0 is defined), start_addr_1 (e.g., start address of Buf_1), and max_addr_1 (e.g., maximum read address where the allocated fragment Buf_1 is defined).

The NDMA core 710 may be configured to automatically compensate for any read or write access that crosses a minimum access length (MAL) boundary on a read/write path. The MAL boundary may be based on a page size of the external memory 760. According to aspects of the present disclosure, a read/write transaction that crosses a MAL boundary is broken into two transactions to fit into the MAL boundary. Breaking transactions to fit within MAL boundaries is generally performed at the expense of increased transaction overhead. In operation, a MAL alignment is performed for an NDMA read/write transaction at the start of a Dim0 line where the previous line could potentially reside at a MAL misaligned address.

According to aspects of the present disclosure, NDMA software is configured with prior knowledge of MAL attributes of the memory (e.g., external memory 760) in which the NDMA core 710 reads from/writes to for avoiding significant performance impacts. In particular, software users should strictly follow recommendations for burst length and MAL settings for achieving increased access efficiency of the external memory 760. For example, NDMA reads/writes are set to a default 256-bit MAL alignment. To increase memory access efficiency, a 512-bit MAL will specify setting the burst length to a value of four or eight; a 1024-bit MAL will specify setting the burst length to a value of eight. If burst length is set to less than recommended settings, a user may disable MAL alignment circuitry to avoid frequent transaction breaks. In addition, a Dim0 line size is set to a predetermined size for matching the MAL setting and the burst length.

The NDMA core 710 is also configured to support a partial reset operation according to aspects of the present disclosure. For example, an inference result may be determined prior to processing all requested NDMA data of a last network layer. In this case, a partial reset operation may be triggered. In one configuration, detection of a partial reset operation/command triggers the NDMA core 710 to abort all NDMA transactions and clear all pipes. For example, the NDMA core 710 may clear all pipes by flushing read channel(s) and awaiting completion of write transactions. The partial reset may be configured according to an NDMA_rst_req parameter (e.g., NDMA rest request to abort NDMA) and a NDMA_rst_ack parameter (e.g., a pulse to indicate a data path is ready for global reset). When an NDMA_res_req signal is asserted, the NDMA core 710 is triggered to stop sending or receiving data. In addition, the NDMA core 710 is triggered to wait for all outstanding transactions to complete. Once completed, the NDMA core 710 asserts an NDMA_rst_ack signal to the controller 770.

FIG. 9 is a block diagram, illustrating a 3D data structure 900, in which a data concatenation operation is performed, according to aspects of the present disclosure. The NDMA core 710 of FIG. 7 may be configured to improve memory access efficiency by increasing a transaction size. The transaction size may be increased by enlarging an x_size_dword parameter (e.g., the word size of the block 590 of the stripe image 560 in FIG. 5C). Increasing the transaction size provides several benefits, such as improving efficiency and reducing latency when moving NDMA data between the external memory 760 and the NDMA core 710 (shown in FIG. 7). Unfortunately, increasing the transaction size by enlarging the x_size_dword parameter is generally prohibited due to address hopping for streaming blocks of stripe data.

According to aspects of the present disclosure, a transaction size is increased by introducing a cx_size_dword parameter (e.g., the number of dwords of a concatenated line). The c_x_size_dword parameter enables concatenating multiple dwords in a concatenated line. The c_x_size_dword parameter is computed as follows:

c_x_size_dword=(x_size_dword+1)*(dim1_blk_size+1)−1  (1)

For example, as shown in FIG. 9, the 3D data structure 900 includes a first tensor 910 and a second tensor 920. In this configuration, portions (e.g., blocks) of the first tensor 910 and the second tensor 920 are contiguous in a channel direction 902, but represent separate tensors. By increasing the transaction size (e.g., c_x_size_dword) according to EQUATION (1), an NDMA concatenate command may be issued to retrieve the entirety of the first tensor 910 or the second tensor 920, rather than issuing multiple NDMA commands. In addition, the NDMA core 710 also supports a re-concatenate command that allows concatenation of blocks across different DimX directions (e.g., Dim0-Dim1 direction or the channel direction 902). For example, a re-concatenate NDMA command may be issued to read and combine the first tensor 910 and the second tensor 920, if desired by a network layer operation (e.g., convolution). The re-concatenated NDMA data may be written to local storage (e.g., the read buffer 722 of the NDMA core 710).

Transparently combining NDMA transactions by issuing an NDMA concatenate command/NDMA re-concatenate command beneficially reduces the number of transactions issued to the external memory 760. In addition, transparently combining NDMA transactions by issuing an NDMA concatenate command/re-concatenate command also increases throughput as well as computations by increases in the amount of NDMA data (e.g., tensors) available for the read client RCLT and the write client WCLT of the NPU 700 of FIG. 7.

The NDMA core 710 is also configured to support a multi-block operation mode, according to aspects of the present disclosure. In the multi-block operation mode, the NDMA core 710 finishes all blocks specified by an NDMA command before arbitration to other channels is performed. In normal operation, the NDMA core 710 performs data movement in units of one full block for each NDMA channel. At the end of each block, a round robin arbitration is performed for granting of an NDMA channel to move a subsequent block. The multi-block mode supports delaying arbitration for an NDMA channel until a predetermined number of data blocks are read and/or written to/from the read client and/or the write client. In the multi-block operation mode, a num_multi_blk parameter may be programmed to specify the number of blocks transferred in one NDMA channel before arbitration to use other NDMA channels is performed. The multi-block operation mode also beneficially reduces the number of NDMA transactions to the external memory 760.

FIG. 10 is a block diagram, illustrating a memory 1000, in which data compression is performed using a deep learning bandwidth compression (DLBC) operation mode, according to aspects of the present disclosure. The NDMA core 710 is also configured to support the DLBC block 752 of the NoC 750 (of FIG. 7) by prefetching metadata describing the DLBC compression, according to aspects of the present disclosure. In the DLBC operation mode, the DLBC block 752 compresses data on a tile by tile basis, attaining compression ratios of, for example, 8:1 through 8:8.

As shown in the memory 1000, the DLBC block 752 compresses 256-bit tiles 1010 (e.g., NDMA data) to form compressed tiles 1020 along address 1002 of the memory 1000. Compression of the data in the memory 1000 results in gaps of unused data (e.g., 1030, 1032, 1034, 1036, and 1038). In the DLBC compression mode, the DLBC block 752 stores metadata describing the compression ratio of each of the compressed tiles 1020. This metadata is written out when compressing a 256-bit tile, and used by the DLBC block 752 to unpack the tile. For example, one byte of metadata is specified for each of the compressed tiles 1020.

FIGS. 11A and 11B are block diagrams of 3D data structures illustrating a partial stripe mode, according to aspects of the present disclosure. In normal operation, the NDMA core 710 is configured to stream blocks of a full stripe 1110 in response to an NDMA command, as shown in a 3D structure 1100 of FIG. 11A. As shown in a 3D data structure 1150 of FIG. 11B, when the partial stripe mode is enabled, the NDMA core 710 moves all blocks of a partial stripe 1160 before starting arbitration for an NDMA channel. In one configuration, only a last block (e.g., an end of block (eob) of the partial stripe 1160) will be sent out to the client (e.g., read client RCLT or the write client WCLT).

In this aspect of the present disclosure, the partial stripe mode varies according to a slide direction parameter (e.g., slide_dir). If the slide direction parameter is set to the Dim0 direction, when one partial stripe movement is finished in the Dim0 direction, it then goes in the Dim1 direction. After reaching the end of the partial stripe 1160 in the Dim1 direction of the 3D data structure 1150, it returns to the Dim0 direction of the partial stripe 1160 and then repeats. After reaching the end of the partial stripe 1160 in the Dim0 direction, the whole Dim0/Dim1 traversal sequence of the partial stripe 1160 is repeated. If the slide direction parameter is set to the Dim1 direction, when one partial stripe movement of the partial stripe 1160 is finished in the Dim1 direction, the partial stripe movement of the partial stripe 1160 in the Dim1 direction is repeated. After reaching the end of the partial stripe 1160 in the Dim1 direction, it returns to the Dim1 direction of the partial stripe 1160 and then repeated. After reaching the end of the partial stripe 1160 in the Dim1 direction, the whole Dim1/Dim0 traversal sequence of the partial stripe 1160 is repeated. In this mode, a full partial stripe is finished before starting another partial stripe.

According to aspects of the present disclosure, software is used to program hardware configuration registers to direct the NDMA core 710 to perform hardware-based memory bandwidth optimization for NPU direct memory access (NDMA), for example, as described in FIG. 12.

FIG. 12 illustrates a method for hardware-based memory bandwidth optimization of neural processing unit (NPU) direct memory access (NDMA), in accordance with aspects of the present disclosure. A method 1200 begins at block 1202, in which configuration registers of a neural processing unit (NPU) direct memory access (NDMA) core are programmed for a read client and/or a write client. NDMA software may be configured for programming configuration registers of the NDMA core 710 (FIG. 7). The read client and/or the write client may be compute units of the NPU 700 shown in FIG. 7. At block 1204, NDMA transaction requests from the read client and/or the write client are transparently combined as a single NDMA transaction request. At block 1206, data blocks of data stripes from the single NDMA transaction request are streamed to/from an external memory of the NDMA core to/from the read client and/or the write client. For example, FIG. 7 shows streaming of a data stripe to/from the external memory 760. In particular, data blocks are streamed between the read client RCLT and/or write client WCLT to/from the external memory 760. In addition, transparent combining of NDMA data may be performed as shown in FIGS. 8 and 9.

FIG. 13 illustrates a method for hardware-based memory bandwidth optimization of neural processing unit (NPU) direct memory access (NDMA), in accordance with aspects of the present disclosure. A method 1300 begins at block 1302, in which a neural processing unit (NPU) direct memory access (NDMA) core is idle after power up. At block 1304, an NDMA core determines whether a new NPU direct memory access (NDMA) command is received. Once received, at block 1306, configuration registers are programmed to define, for example, image information, bus information, and address information. Once programmed, at block 1308, a load command pulse is generated. In response, at block 1310, client arbitration is initiated. Once initiated, at block 1312, it is determined whether a client buffer is ready. Once the client buffer is ready, at block 1314, it is determined whether an arbitration grant (arb_gnt) is received.

For example, as shown in FIG. 7, detection of the load command for either the read client RCLT or the write client WCLT triggers initial arbitration using the read arbiter 712 or the write arbiter 714. While the arbitration is requested, the NDMA core determines whether the client buffer of the read client RCLT or the write client WCLT is ready depending on whether the read client RCLT or the write client WCLT is the target of the load command.

Referring again to FIG. 13, once the arbitration is granted, at block 1316, transparent combining of NDMA transaction requests into a single NDMA transaction request is performed. For example, as shown in FIG. 8, the read engine 720 is configured to independently perform a stripe image read from a scattered memory location (e.g., NDMA data blocks), such that scattered locations of external memory 760 appear as one contiguous space for the read client RCLT. In this aspect of the present disclosure, the method 1300 includes combining blocks of NDMA data from scattered memory locations of the external memory as a contiguous address space for the read client. As shown in FIG. 9, an NDMA concatenate command may be issued to retrieve the entirety of the first tensor 910 or the second tensor 920, rather than issuing multiple NDMA commands.

During normal operation, one block of NDMA data is processed for each bus transaction. In addition, the single NDMA command involves stripe data that is provided by streaming the data blocks of the stripe data. In the memory bandwidth optimization mode, as shown in FIG. 13, at block 1318, it is determined whether the single NDMA transaction is complete. Once the transaction is completed, the method 1300 returns to the idle state at block 1302 until another NDMA command is received.

In some aspects, the methods 1200, 1300 may be performed by the NPU 108 (FIG. 1) and/or the NPU 700 (FIG. 7). That is, each of the elements of methods 1200, 1300 may, for example, but without limitation, be performed by the NPU 108 or the NPU 700, including the NDMA core 710 and/or other components included therein.

Aspects of the present disclosure are directed to a neural processing unit (NPU) direct memory access (NDMA) hardware-based optimization for convolutional neural networks. NDMA moves NDMA data from main memory to storage closer to the compute units of an NPU for local storage. In aspects of the present disclosure, transactions requesting NDMA data may be transparently combined into a single NDMA transaction, with the requested NDMA data stored into NDMA queues. Transparently combining transactions requesting NDMA data beneficially reduces the number of transactions issued to the external memory. Transparently combining NDMA transactions also increases throughput as well as computations by increasing the amount of NDMA data (e.g., tensors) available for NPU operations.

An artificial neural network model includes means for programming, means for transparently combining, and/or means for streaming. In one aspect, the programming means, the transparently combining means, and/or the streaming means may be the NPU 108, program memory associated with the NPU 108, the memory block 118, the NPU 700, and/or the NDMA core 710 configured to perform the functions recited. The means for means for transparently combining NDMA transaction requests includes means for combining blocks of NDMA data, means for concatenating data blocks of data stripes, means for re-concatenating data blocks of data stripes, and/or means for delaying arbitration. In one aspect, the combining means, the concatenating means, the re-concatenating means and/or the delaying means may be the NPU 108, program memory associated with the NPU 108, the memory block 118, the NPU 700, and the NDMA core 710 configured to perform the functions recited. In another configuration, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to, a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in the figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining, and the like. Additionally, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Furthermore, “determining” may include resolving, selecting, choosing, establishing, and the like.

As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.

The various illustrative logical blocks, modules, and circuits described in connection with the present disclosure may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) signal, or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, and so forth. A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a device. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement signal processing functions. For certain aspects, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.

The processor may be responsible for managing the bus and general processing, including the execution of software stored on the machine-readable media. The processor may be implemented with one or more general-purpose and/or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Machine-readable media may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product. The computer-program product may comprise packaging materials.

In a hardware implementation, the machine-readable media may be part of the processing system separate from the processor. However, as those skilled in the art will readily appreciate, the machine-readable media, or any portion thereof, may be external to the processing system. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the device, all which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files. Although the various components discussed may be described as having a specific location, such as a local component, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.

The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may comprise one or more neuromorphic processors for implementing the neuron models and models of neural systems described herein. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) with the processor, the bus interface, the user interface, supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.

The machine-readable media may comprise a number of software modules. The software modules include instructions that, when executed by the processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module. Furthermore, it should be appreciated that aspects of the present disclosure result in improvements to the functioning of the processor, computer, machine, or other system implementing such aspects.

If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a non-transitory computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Additionally, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media). In addition, for other aspects computer-readable media may comprise transitory computer-readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.

Thus, certain aspects may comprise a computer program product for performing the operations presented herein. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. For certain aspects, the computer program product may include packaging material.

Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device can be utilized.

It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims. 

What is claimed is:
 1. A neural processing unit (NPU), comprising: an NPU direct memory access (NDMA) core comprising: a read engine having a read buffer; and a write engine having a write buffer; and a controller configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer, the NDMA core configured to transparently combine NDMA transaction requests for a data stripe.
 2. The NPU of claim 1, in which the controller is configured to direct the NDMA core to pre-fetch deep learning bandwidth compression (DLBC) metadata when NDMA data is compressed by a DLBC block of a network on chip (NoC) coupled between an external memory and the NDMA core.
 3. The NPU of claim 1, in which the controller is configured to direct the NDMA core to combine blocks of NDMA data from scattered memory locations of an external memory as a contiguous address space for a read client.
 4. The NPU of claim 3, in which the controller is configured to direct the NDMA core to split NDMA read and/or NDMA write transactions that cross a minimum access length (MAL) boundary of the external memory.
 5. The NPU of claim 1, further comprising a read client coupled to an interface of the read engine of the NDMA core and a write client coupled to an interface of the write engine of the NDMA core.
 6. The NPU of claim 1, further comprising: a read arbiter coupled to the read engine; a write arbiter coupled to the write engine; and an external memory coupled to the read arbiter and the write arbiter.
 7. The NPU of claim 6, further comprising a bus bridge coupled between the external memory and the read arbiter and the write arbiter.
 8. The NPU of claim 7, further comprising a network on chip (NoC) coupled between the external memory and the bus bridge.
 9. The NPU of claim 1, further comprising: a write client coupled to a first memory interface of the NDMA core; and a read client coupled to a second memory interface of the NDMA core.
 10. The NPU of claim 9, in which the write client and the read client comprise a client buffer used to store DMA data of the NDMA core.
 11. A method for hardware-based memory bandwidth optimization of a neural processing unit (NPU) direct memory access (NDMA) in artificial neural networks, comprising: programming configuration registers of a neural processing unit (NPU) direct memory access (NDMA) core for a read client and/or a write client; transparently combining NDMA transaction requests from the read client and/or the write client as a single NDMA transaction request; and streaming data blocks of data stripes of the single NDMA transaction request, the data blocks being streamed to/from an external memory of the NDMA core and to/from the read client and/or the write client.
 12. The method of claim 11, in which the transparently combining NDMA transaction requests comprises combining blocks of NDMA data from scattered memory locations of the external memory as a contiguous address space for the read client.
 13. The method of claim 11, in which the transparently combining NDMA transaction requests further comprises concatenating the data blocks of the data stripes using an increased transaction size.
 14. The method of claim 13, further comprising re-concatenating the data blocks of the data stripes at interleaved locations of a read buffer of the read client and/or a write buffer of the write client.
 15. The method of claim 11, in which the transparently combining NDMA transaction requests further comprises delaying arbitration for an NDMA channel until a predetermined number of the data blocks are read and/or written to/from the read client and/or the write client.
 16. An artificial neural network for hardware-based memory bandwidth optimization of a neural processing unit (NPU) direct memory access (NDMA), the artificial neural network comprising: means for programming configuration registers of a neural processing unit (NPU) direct memory access (NDMA) core for a read client and/or a write client; means for transparently combining NDMA transaction requests from the read client and/or the write client as a single NDMA transaction request; and means for streaming data blocks of data stripes of the single NDMA transaction request, the data blocks of data stripes being streamed to/from an external memory of the NDMA core and to/from the read client and/or the write client.
 17. The artificial neural network of claim 16, in which the means for transparently combining NDMA transaction requests comprises means for combining blocks of NDMA data from scattered memory locations of the external memory as a contiguous address space for the read client.
 18. The artificial neural network of claim 16, in which the means for transparently combining NDMA transaction requests further comprises means for concatenating data blocks of data stripes using an increased transaction size.
 19. The artificial neural network of claim 18, further comprising means for re-concatenating data blocks of data stripes at interleaved locations of a read buffer of the read client and/or a write buffer of the write client.
 20. The artificial neural network of claim 16, in which the means for transparently combining NDMA transaction requests further comprises means for delaying arbitration for an NDMA channel until a predetermined number of data blocks are read and/or written to/from the read client and/or the write client.
 21. A non-transitory computer-readable medium having program code recorded thereon for hardware-based memory bandwidth optimization of a neural processing unit (NPU) direct memory access (NDMA), the program code being executed by a processor and comprising: program code to program configuration registers of a neural processing unit (NPU) direct memory access (NDMA) core for a read client and/or a write client; program code to transparently combine NDMA transaction requests from the read client and/or the write client as a single NDMA transaction request; and program code to stream data blocks of data stripes of the single NDMA transaction request, data blocks of data stripes being streamed to/from an external memory of the NDMA core and to/from the read client and/or the write client.
 22. The non-transitory computer-readable medium of claim 21, in which the program code to transparently combine NDMA transaction requests comprises program code to combine blocks of NDMA data from scattered memory locations of the external memory as a contiguous address space for the read client.
 23. The non-transitory computer-readable medium of claim 21, in which the program code to transparently combine NDMA transaction requests further comprises program code to concatenate the data blocks of the data stripes using an increased transaction size.
 24. The non-transitory computer-readable medium of claim 23, further comprising program code to re-concatenate the data blocks of the data stripes at interleaved locations of a read buffer of the read client and/or a write buffer of the write client.
 25. The non-transitory computer-readable medium of claim 21, in which the program code to transparently combine NDMA transaction requests further comprises program code to delay arbitration for an NDMA channel until a predetermined number of the data blocks are read and/or written to/from the read client and/or the write client. 